View AOZ1092DI_8149418.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.3 february 2009 www.aosmd.com page 1 of 16 aoz1092d ezbuck? 3a simple buck regulator general description the aoz1092d is a high efficiency, simple to use, 3a buck regulator. the aoz1092d works from a 4.5v to 16v input voltage range, and provides up to 3a of continuous output current with an output voltage adjustable down to 0.8v. the aoz1092d comes in 4x5 dfn-8 packages and is rated over a -40c to +85c ambient temperature range. features 4.5v to 16v operating input voltage range 50m ? internal pfet switch for high efficiency: up to 95% schottky diode is included internal soft start output voltage adjustable to 0.8v 3a continuous output current fixed 500khz pwm operation cycle-by-cycle current limit short-circuit protection output over voltage protection thermal shutdown small size 4x5 dfn-8 packages applications point of load dc/dc conversion pcie graphics cards set top boxes dvd drives and hdd lcd panels cable modems telecom/networking/datacom equipment typical application figure 1. 3.3v/3a non-synchronous buck regulator lx vin u1 vin fb gnd en comp agnd c1 22f ceramic c5 c2, c3 22f ceramic vout 3.3v r1 r2 l1 4.7h aoz1092d r c c c
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 2 of 16 ordering information all aos products are offering in packaging with pb -free plating and compliant to rohs standards. please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. pin configuration pin description part number ambient temperature range package environmental AOZ1092DI -40c to +85c dfn-8 4x5 rohs pin number pin name pin function 1v in supply voltage input. when v in rises above the uvlo threshold the device starts up. 2 pgnd power ground. electrically needs to be connected to agnd. 3 agnd reference connection for controller section. also used as thermal connecti on for controller section. electrically needs to be connected to pgnd. 4 fb the fb pin is used to determine the output volt age via a resistor divider between the output and gnd. 5 comp external loop compensation pin. 6 en the enable pin is active high. connect en pin to v in if not used. do not leave the en pin floating. 7, 8 lx pwm output connection to inductor. thermal connection for output stage. vin pgnd agnd fb lx lx en comp 4x5 dfn (top view) 1 2 3 4 8 7 6 5 gnd lx
rev. 1.3 february 2009 www.aosmd.com page 3 of 16 aoz1092d block diagram absolute maximum ratings exceeding the absolute maxi mum ratings may damage the device. recommend operating ratings the device is not guaranteed to operate beyond the maximum operating ratings. 500khz/63khz oscillator agnd pgnd vin en fb comp lx otp internal +5v ilimit pwm control logic 5v ldo regulator uvlo & por softstart reference & bias 0.8v q1 d1 pwm comp level shifter + fet driver isen eamp 0.2v + ? + ? + ? + ? + 0.96v + ? frequency foldback comparator over voltage protection comparator parameter rating supply voltage (v in ) 18v lx to agnd -0.7v to v in +0.3v en to agnd -0.3v to v in +0.3v fb to agnd -0.3v to 6v comp to agnd -0.3v to 6v pgnd to agnd -0.3v to 0.3v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c parameter rating supply voltage (v in ) 4.5v to 16v output voltage range 0.8v to v in ambient temperature (t a ) -40c to +85c package therma l resistance dfn 4x5 ( ja ) 53c/w
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 4 of 16 electrical characteristics t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. (3) note: 3. specifications in bold indicate an ambient temperature range of -40c to +85c. these specifications are guaranteed by design. symbol parameter conditions min. typ. max. units v in supply voltage 4.5 16 v v uvlo input under-voltage lockout threshold v in rising v in falling 4.00 3.70 v i in supply current (quiescent) i out = 0, v fb = 1.2v, v en > 1.2v 23 ma i off shutdown supply current v en = 0v 110 a v fb feedback voltage 0.782 0.8 0.818 v load regulation 0.5 % line regulation 0.5 % i fb feedback voltage input current 200 na enable v en en input threshold off threshold on threshold 2.0 0.6 v v hys en input hysteresis 100 mv modulator f o frequency 400 500 600 khz d max maximum duty cycle 100 % d min minimum duty cycle 6% g vea error amplifier voltage gain 500 v / v g ea error amplifier transconductance 200 a / v protection i lim current limit 4 5 a v pr output over-voltage protection threshold off threshold on threshold 960 840 mv t j over-temperature shutdown limit 150 c t ss soft start interval 2.2 ms output stage high-side switch on-resistance v in = 12v v in = 5v 40 65 50 85 m ?
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 5 of 16 typical performance characteristics circuit of figure 1. t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. startup to full load full load to turn off 50% to 100% load transient no load to turn off 1 s/di v 1 s/di v 400 s/di v 1ms/di v 100 v 1s/di v v in ripple 50m v /di v v o ripple 50m v /di v v o 2 v /di v v in 5 v /di v lin 1a/di v v o 1 v /di v v in 5 v /di v lin 1a/di v v o 1 v /di v v in 5 v /di v lin 1a/di v v o ripple 0.1 v /di v lo 2a/di v il 2a/di v v lx 10 v /di v v in ripple 0.1 v /di v v o ripple 50m v /di v il 2a/di v v lx 10 v /di v light load (dcm) operation full load (ccm) operation
rev. 1.3 february 2009 www.aosmd.com page 6 of 16 aoz1092d typical performance characteristics (continued) circuit of figure 1. t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. efficiency thermal derating curves thermal derating curves for 4x5 dfn-8 package part under typical line and output voltage condition based on eval board. circuit of figure 1. 25c ambient temper ature and natural convection (air speed <50lfm) unless otherwise specified. 100 s/di v 1ms/di v v o 2 v /di v il 2a/di v v o 2 v /di v il 2a/di v short circuit protection short circuit recovery efficiency (v in = 12v) vs. load current 75 80 85 90 95 5.0v output 3.3v output 8.0v output 100 0 0.5 1.0 1.5 2.0 2.5 3.0 load current (a) efficieny (%) derating curve at 5v/6v input 5.0v output 1.8v output 3.3v output ambient temperature (t a ) output current (i o ) 3.5 3.0 2.5 2.0 1.5 1.0 25 35 45 55 65 75 85 derating curve at 12 input 1.8v output 8.0v output ambient temperature (t a ) output current (i o ) 3.5 3.0 2.5 2.0 1.5 1.0 25 35 45 55 65 75 85 3.3v output 5.0v output
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 7 of 16 detailed description the aoz1092d is a current-mode step down regulator with integrated high side pmos switch and low side schottky diode. it operates from a 4.5v to 16v input voltage range and supplies up to 3a of load current. the duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltage. features include enable control, power-on reset, input under voltage lockout, fixed internal soft-start and thermal shut down. the aoz1092d is available in 4x5 dfn-8 package. enable and soft start the aoz1092d has internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft start process begins when the input voltage rises to 4.0v and voltage on en pin is high. in soft start process, the output voltage is ramped to regulation voltage in typically 2.2ms. the 2.2ms soft start time is set internally. the en pin of the aoz1092d is active high. connect the en pin to vin if enable function is not used. pull it to ground will disable the aoz1092 d. do not leave it open. the voltage on en pin must be above 2.0 v to enable the aoz1092d. when voltage on en pin falls below 0.6v, the aoz1092d is disabled. steady-state operation under steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). the aoz1092d integrates an internal p-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is amplified by the internal transconductance error amplifier. the error voltage, which shows on the comp pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at pwm comparator input. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current flows from the input through the inductor to the output. when the current signal exceeds the error voltage, the high-side switch is off. the inductor current is freewheeling through the internal schottky diode to output. the aoz1092d uses a p-channel mosfet as the high side switch. it saves the boo tstrap capacitor normally seen in a circuit which is using an nmos switch. it allows 100% turn-on of the upper switch to achieve linear regu- lation mode of operation. the minimum voltage drop from v in to v o is the load current times dc resistance of mosfet plus dc resistance of buck inductor. it can be calculated by equation below: where; v o_max is the maximum output voltage, v in is the input voltage from 4.5v to 16v, i o is the output current from 0a to 3a, r ds(on) is the on resistance of in ternal mosfet, the value is between 40m ? and 70m ? depending on input voltage and junction temperature, and r inductor is the inductor dc resistance. switching frequency the aoz1092d switching frequency is fixed and set by an internal oscillator. the practical switching frequency could range from 400khz to 600khz due to device variation. output voltage programming output voltage can be set by feeding back the output to the fb pin with a resistor divider network. in the application circuit shown in figure 1. the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a fixed r 2 value and calculating the required r 1 with equation below. some standard value of r 1 , r 2 and most commonly used output voltage values are listed in table 1. the combination of r 1 and r 2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. v o (v) r 1 (k ? ) r 2 (k ? ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.1 10 5.0 52.3 10 v o_max v in i o r ds on () r inductor + () ? = v o 0.8 1 r 1 r 2 ------ - + ?? ?? ?? =
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 8 of 16 since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper pmos and inductor. protection features the aoz1092d has multiple protection features to prevent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current signal is also used for over current protection. since aoz1092d employs peak current mode control, the comp pin voltage is proportional to the peak inductor current. the comp pin voltage is limited to be between 0.4v and 2.5v internally. the peak inductor current is automatically limited cycle by cycle. the cycle by cycle current limit threshold is set between 4a and 5a. when the load current reaches the current limit threshold, the cycle by cy cle current limit circuit turns off the high side switch immediately to terminate the current duty cycle. the inductor current stop rising. the cycle by cycle current limit protection directly limits inductor peak current. the average inductor current is also limited due to the limitation on peak inductor current. when cycle by cycle current limit circuit is triggered, the output voltage drops as the duty cycle decreasing. the aoz1092d has internal short circuit protection to protect itself from catastrophic failure under output short circuit conditions. the fb pin voltage is proportional to the output voltage. whenever fb pin voltage is below 0.2v, the short circuit protecti on circuit is triggered. as a result, the converter is shut down and hiccups at a frequency equals to 1/8 of normal switching frequency. the converter will start up via a soft start once the short circuit condition disappears. in short circuit protection mode, the inductor average current is greatly reduced because of the low hiccup frequency. power-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4v, the converter starts operation. when input volt age falls below 3.7v, the converter will be shut down. output over voltage protection (ovp) the aoz1092d monitors the feedback voltage: when the feedback voltage is higher than 960mv, it immediate turns-off the pmos to pr otect the output voltage overshoot at fault condition. when feedback voltage is lower than 840mv, the pmos is allowed to turn on in the next cycle. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and high side pmos if the junction temperature exceeds 150oc. application information the basic aoz1092d application circuit is shown in figure 1. component selection is explained below. input capacitor the input capacitor must be connected to the v in pin and pgnd pin of the aoz1092d to maintain steady input voltage and filter out the pulsing input current. the voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. the input ripple voltage can be approximated by equation below: since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of input capacitor current can be calculated by: if let m equal the conversion ratio: the relationship between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2 below. it can be seen that when v o is half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5 x i o . figure 2. i cin vs. voltage conversion ratio v in i o fc in ----------------- 1 v o v in -------- - ? ?? ?? ?? v o v in -------- - = i cin_rms i o v o v in -------- - 1 v o v in -------- - ? ?? ?? ?? = v o v in -------- - m = 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 9 of 16 for reliable operation and best performance, the input capacitors must have current rating higher than i cin_rms at worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high ripple current rating. depending on the application circuits, other low esr tantalum capacitor or aluminum electrolytic capacitor may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. note that the ripple current rating from capacitor manufactures are based on certain amount of life time. further de-rating may be necessary for practical design requirement. inductor the inductor is used to supply constant current to output when it is driven by a swit ching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: the peak inductor current is: high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low ripple current reduces inductor core losses. it also reduces rms current through inductor and switches, which results in less conduction loss. when selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor needs to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. table 2 lists some inductors for typical output voltage design. table 2. output capacitor the output capacitor is select ed based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacito r must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be considered for long term reliability. output ripple voltage specif ication is another important factor for selecting the outp ut capacitor. in a buck con- verter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and esr. it can be calculated by the equation below: where, c o is output capacitor value, and esr co is the equivalent series resistance of the output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: i l v o fl ---------- - 1 v o v in -------- - ? ?? ?? ?? = i lpeak i o i l 2 -------- + = v out l1 manufacturer 5.0v shielded, 6.8h mss1278-682mld coilcraft shielded, 6.8h mss1260-682mld 3.3v un-shielded, 4.7h do3316p-472mld coilcraft shielded, 4.7h do1260-472nxd shielded, 3.3h et553-3r3 elytone 1.8v shielded, 2.2h et553-2r2 elytone un-shielded, 3.3h do3316p-222mld coilcraft shielded, 2.2h mss1260-222nxd v o i l esr co 1 8 fc o ------------------------- + ?? ?? = v o i l 1 8 fc o ------------------------- ?? ?? =
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 10 of 16 if the impedance of esr at switching frequency dominates, the output ripple vo ltage is mainly decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum capacitor or aluminum electrolytic capacitor may also be used as output capacitors. in a buck converter, out put capacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. loop compensation the aoz1092d employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the doubl e pole effect of the output l&c filter. it greatly simp lifies the compensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole and can be calculated by: the zero is a esr zero due to output capacitor and its esr. it is can be calculated by: where; c o is the output filter capacitor, r l is load resistor value, and esr co is the equivalent series resistance of output capacitor. the compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. several different types of compensation network can be used for the aoz1092d. for most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in the aoz1092d, fb pin and comp pin are the invert- ing input and the output of internal transconductance error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: where; g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, g vea is the error amplifier voltage gain, which is 500 v/v, and c c is cthe compensation capacitor. the zero given by the external compensation network, capacitor c c and resistor r c , is located at: to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover frequency is also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high because of system stability concern. when designing the compensation loop, converter stability under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be less than 1/10 of switching frequency. the aoz1092d operates at a fixed switching frequency range from 400khz to 600khz. it is recommended to choose a crossover frequency less than 50khz. the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected crossover frequency, f c , to calculate r c : v o i l esr co = i co_rms i l 12 ---------- = f p 1 1 2 c o r l ---------------------------------- - = f z 1 1 2 c o esr co ------------------------------------------------ = f p 2 g ea 2 c c g vea ------------------------------------------ - = f z 2 1 2 c c r c ----------------------------------- = f c 50 khz = r c f c v o v fb ---------- 2 c o g ea g cs ----------------------------- - =
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 11 of 16 where; where f c is desired crossover frequency, v fb is 0.8v, g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, and g cs is the current sense circuit tr ansconductance, which is 6.86 a/v the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected cross- over frequency. c c can is selected by: the above equation can be simplified to: an easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com . thermal management and layout consideration in the aoz1092d buck regulator circuit, high pulsing current flows through two circuit loops. the first loop starts from the input capacitors, to the v in pin, to the lx pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. current flows in the first loop when the high side switch is on. the second loop starts from inductor, to the output capacitors and load, to the anode of schottky diode, to the cathode of schottky diode. current flows in the second loop when the low side diode is on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. a ground plane is strongly recommended to connect input capacitor, output capacitor, and pgnd pin of the aoz1092d. in the aoz1092d buck regulator circuit, the major power dissipating components are the aoz1092d and output inductor. the total power dissipation of converter circuit can be measured by input power minus output power. the power dissipation of inductor can be approximately calculated by output curren t and dcr of the inductor. the actual junction temperature can be calculated with power dissipation in the aoz1092d and thermal impedance from junction to ambient. the maximum junction tem perature of aoz1092d is 150oc, which limits the maxi mum load current capability. please see the thermal de-rating curves for maximum load current of the aoz1092d under different ambient temperature. the thermal performance of the aoz1092d is strongly affected by the pcb layout. extra care should be taken by users during design process to ensure that the ic will operate under the recommended environmental conditions. several layout tips are listed below for the best electric and thermal performance. fi gure 3 on the next page illustrates a pcb layout example as reference. 1. do not use thermal relief connection to the v in and the pgnd pin. pour a maximized copper area to the pgnd pin and the v in pin to help thermal dissipation. 2. input capacitor should be connected to the v in pin and the pgnd pin as close as possible. 3. a ground plane is preferred. if a ground plane is not used, separate pgnd from agnd and connect them only at one point to avoid the pgnd pin noise coupling to the agnd pin. 4. make the current trace from lx pins to l to co to the pgnd as short as possible. 5. pour copper plane on all unused board area and connect it to stable dc nodes, like v in , gnd or v out . 6. the two lx pins are connected to internal pfet drain. they are low resistance thermal conduction path and most noisy switching node. connected a copper plane to lx pin to help thermal dissipation. this copper plane should not be too larger otherwise switching noise may be coupled to other part of circuit. 7. keep sensitive signal trace far away form the lx pins. c c 1.5 2 r c f p 1 ---------------------------------- - = c c c o r l r 3 --------------------- = p total_loss v in i in v o i o ? = p inductor_loss i o 2 r inductor 1.1 = t amb + t junction p total_loss p inductor_loss ? () ja =
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 12 of 16 figure 3. aoz1092d pcb layout lx lx vin pg ag fb en cp cin l cout thermal pad: lx thermal pad: agnd via to ground plane vin vo gnd
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 13 of 16 package dimensions, dfn 4x5 d index area (d/2 x e/2) l r 1 e2 e3 l1 d2 d3 aaa c ccc c ddd c bbb aaa c d/2 e/2 a3 b a1 2.125 1.775 0.6 2.2 0.95 0.5 0.8 2.7 unit: mm a a e b e c cab seating plane pin #1 ida notes: 1. dimensions and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. 3. the location of the terminal #1 identifier and terminal numbering convention conforms to jedec publication 95 sp-002. 4. dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. coplanarity applies to the terminals and all other bottom surface metallization. 6. drawing shown are for illustration only. symbols a a1 a3 b d d2 d3 e e2 e3 e l l1 r aaa bbb ccc ddd dimensions in millimeters recommended land pattern min. 0.80 0.00 0.35 1.975 1.625 2.500 2.050 0.600 0.400 ? ? ? ? nom. 0.90 0.02 0.20 ref 0.40 5.00 bsc 2.125 1.775 4.00 bsc 2.650 2.200 0.95 bsc 0.700 0.500 0.30 ref 0.15 0.10 0.10 0.08 max. 1.00 0.05 0.45 2.225 1.875 2.750 2.300 0.800 0.600 ? ? ? ? symbols a a1 a3 b d d2 d3 e e2 e3 e l l1 r aaa bbb ccc ddd dimensions in inches min. 0.031 0.000 0.014 0.078 0.064 0.098 0.081 0.024 0.016 ? ? ? ? nom. 0.035 0.001 0.008 ref 0.016 0.197 bsc 0.084 0.070 0.157 bsc 0.104 0.087 0.037 bsc 0.028 0.020 0.012 ref 0.006 0.004 0.004 0.003 max. 0.039 0.002 0.018 0.088 0.074 0.108 0.091 0.031 0.024 ? ? ? ?
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 14 of 16 tape dimensions, dfn 4x5 r0.40 p0 k0 a0 e e2 d0 e1 d1 b0 package dfn 5x4 (12 mm) a0 b0 k0 e e1 e2 d0 d1 p0 p1 p2 t 5.30 0.10 0.10 4.30 0.10 1.20 min. 1.50 1.50 12.00 0.10 1.75 0.10 5.50 0.10 8.00 0.20 4.00 0.10 2.00 0.05 0.30 unit: mm t typ. 0.20 feeding direction tape leader/trailer and orientation 0.30 +0.10 / ?0 trailer tape (300mm min.) components tape orientation in pocket leader tape (500mm min.)
rev. 1.3 february 2009 www.aosmd.com page 15 of 16 aoz1092d reel dimensions, dfn 4x5 view: c c 0.05 3-1.8 ?6 ?.2 6.45?.05 3- 2.9 ?.05 3-?/8" 3-?/4" 8.9?.1 11.90 14 ref 1.8 5.0 12 ref 41.5 ref 43.00 44.5?.1 2.00 6.50 10.0 10.71 10 3-?/16" r48 ref ?6.0?.1 2.20 6.2 ?3.00 ?1.20 ?7.0 r1.1 0 r3.10 2.00 3.3 4.0 6.10 0.80 3.00 8.00 +0.05 0.00 r0.5 1.80 2.5 38 44.5?.1 46.0?.1 8.0?.1 40 6 3- 3/16" r3.95 6.50 ?0.00 6.0 1.8 1.8 r1 8.00 0.00 -0.05 n=?00? a a a r121 r127 r159 r6 r55 p b w1 m ii i i 6.0? r1 zoom in iii zoom in ii zoom in a
aoz1092d rev. 1.3 february 2009 www.aosmd.com page 16 of 16 package marking z1092di faywlt part number code assembly lot code fab & assembly location year & week code as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this data sheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products are not author ized for use as critical components in life support devices or systems.

▲Up To Search▲

Price & Availability of AOZ1092DI

	To Download AOZ1092DI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .